Contention among simultaneously arriving packet cells for the same output port of a packet switch is resolved in favor of only one packet cell at a time. As a result, some form of temporary storage is required for the remaining packet cells. Temporary storage provided on the input side of the switch is an input queue whereas storage of the packet cells on the output side of the switch is called an output queue. With respect to each input/output line of the switch, the input queue permits loading up to a maximum of 58% whereas the output queue permits loading up to 100% when the first in, first out (FIFO) storage is utilized.
The reason for such poor performance in input-queued packet switches is related to a problem known a head-of-line blocking. To overcome this problem, it has been proposed that the storage devices in the input queue be non-FIFO or random access. In addition, scheduling of packet cells from different input queues for the same output port is performed in two phases to result in non-conflicting transmission of the packet cells. See, for example, an article by Obara et al., Int'l. J. of Digital and Analog Cabled Systems, Vol. 2, No. 4, pp. 261-7 (1989). This type of scheduling is called output scheduling. It permits improvement of the switch throughput from 58% to 65% for random packet cell traffic models.